The process also ensures that the incremental changes made are identifiable in the netlist to the corresponding netlist import and compile function. Re-synthesis occurs only on those parts of the design that are directly affected by the incremental change. Using compile points, design modifications can be managed without disturbing other parts of the design.ДЄ вЂњdifference-basedвЂќ incremental synthesis process keeps track of design changes and dependencies. Any number of compile points can be identified and nested into the design. Each compile point is treated as an individual block for incremental and individual mapping. (Click this image to view a larger, more detailed version)ДЄlternatively, design teams can work on individual compile points simultaneously and independently. Incremental flow using Synplify Pro and Libero IDE. This implies that all instantiations of the same locked compile point have the same implementation and are treated identically during synthesis.ДЎ. A вЂњlockedвЂќ compile point means that, during synthesis of its parent, it is not re-optimized, its hierarchical interface is unchanged, and no boundary optimizations are made. Compile points are locked, to ensure stability in incremental design and to permit hierarchical place and route with multiple output netlists (one for each compile point and one for the top level of the design).

They are re-synthesized only as needed, based on an analysis of design dependencies and the nature of design changes.

Compile points are parts of a design that act as relatively independent synthesis units: they have their own constraint files and are optimized individually. The design flow ( Fig 1 ) closely resembles a traditional synthesis/physical implementation flow, with the addition of вЂњcompile pointsвЂќ after the initial synthesis project setup and compile. Additionally, the Magma PALACE physical synthesis tool can generally improve the overall performance of Actel's Fusion Programmable System Chips and ProASIC3 devices by a significant margin.Д«ut what if further optimization on segments of the design need to be managed after the initial layout? What if performance is still marginal, or some of the blocks still contain functional problems? For performance improvements, the Actel SmartTime timing analysis and constraints management tool provides features for identifying and resolving critical paths within the design. Using tools from Actel and its partners, the Libero IDE Platinum toolset is well equipped to successfully manage a вЂњright-first-timeвЂќ design. If functional and timing performance requirements are met, a programming file is generated and the device is programmed. Analyze the design's timing performance.The common flow for FPGA development is to:

Traditional design creation and physical implementation Other design strategies involve freezing sections of a completed design while other parts of the design are continuing development independently. When a top-down design approach is difficult due to system memory limitations or extensive run times, an incremental design flow also enables designers to process large designs. Compared with a traditional flow, an вЂњincrementalвЂќ design flow for design/synthesis and place-and-route physical implementation is highly desirable with regard to repairing or optimizing specific parts of the design without disturbing other portions that have met their design requirements. Regardless of the amount of time and energy FPGA designers invest attempting to create вЂњright-first-timeвЂќ designs, the functional complexities, performance requirements, and high gate counts of large complex designs frequently require changes to correct logic problems or to provide further optimization.

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